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Stacked chip-scale package (SCSP) is a type of chip-scale packaging that combines multiple silicon dice stacked on top of one another in one molded package. When SCSP was introduced to the factory of the author, margin delta failures increased significantly. Margin delta is a post-burn-in electrical test parameter that indicates the charge loss and gain in the main array of Flash memory. Subsequent failure analysis (FA) showed that these margin delta failures are due to a circular defect on the surface passivation of the bottom die. This paper presents a new failure analysis approach for isolating this passivation damage. The conventional technique for analyzing passivation damage of this nature involves bottom die recovery, which consists of grinding the top die down to its die attach material, and doing a wet etch to expose the surface of the bottom die. This study presents the 'backside thinning approach' as an alternative approach for analyzing passivation damage. The backside thinning approach preserves the defect embedded in the passivation layer, which can be lost if the bottom die recovery technique is used. Backside thinning basically consists of grinding the SCSP from its solder balls down to the bottom die's layer of interest to find the defect. SEM/EDX and FIB techniques are then employed to complete the FA. This study confirmed the effectiveness of the backside thinning approach, which successfully identified the silver particles of the die attach material of the top die as the cause of the passivation damage.
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