Crystal Defects in Silicon - Page 2 of 3 - Line Defects or Dislocations

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Crystalline Defects in Silicon (Page 2 of 3)

Crystal line defects are also known as 'dislocations', which can be classified as one of the following: 1) edge dislocation; 2) screw dislocation; or 3) mixed dislocation, which contains both edge and screw dislocation components.

An edge dislocation may be described as an extra plane of atoms squeezed into a part of the crystal lattice, resulting in that part of the lattice containing extra atoms and the rest of the lattice containing the correct number of atoms. The part with extra atoms would therefore be under compressive stresses, while the part with the correct number of atoms would be under tensile stresses. The dislocation line of an edge dislocation is the line connecting all the atoms at the end of the extra plane.

Figure 1. An edge dislocation; note the insertion

of atoms in the upper part of the lattice

If the dislocation is such that a step or ramp is formed by the displacement of atoms in a plane in the crystal, then it is referred to as a 'screw dislocation.' The screw basically forms the boundary between the slipped and unslipped atoms in the crystal. Thus, if one were to trace the periphery of a crystal with a screw dislocation, the end point would be displaced from the starting point by one lattice space. The dislocation line of a screw dislocation is the axis of the screw.

Figure 2. A screw dislocation; note the screw-like

'slip' of atoms in the upper part of the lattice

If the dislocation consists of an extra plane of atoms (or a missing plane of atoms) lying entirely within the crystal, then the dislocation is known as a 'dislocation loop.' The dislocation line of a dislocation loop forms a closed curve that is usually circular in shape, since this shape results in the lowest dislocation energy.

Dislocations are generally undesirable in silicon wafers because they serve as sinks for metallic impurities as well as disrupt diffusion profiles. However, the ability of dislocations to sink impurities may be engineered into a wafer fabrication advantage. i.e., it may be used in the removal of impurities from the wafer, a technique known as 'gettering.'

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