CSP - Chip Scale Package

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Chip Scale Package (CSP)

Chip Scale Package, or CSP, based on IPC/JEDEC J-STD-012 definition, is a single-die, direct surface mountable package with an area of no more than 1.2 X the original die area. The acronym 'CSP' used to stand for 'Chip Size Package,' but very few packages are in fact the size of the chip, hence the wider definition released by IPC/JEDEC.

The IPC/JEDEC definition likewise doesn't define how a chip scale package is to be constructed, so any package that meets the surface mountability and dimensional requirements of the definition is a CSP, regardless of structure. For this reason, CSP's come in many forms - flip-chip, non-flip-chip, wire-bonded, ball grid array, leaded, etc.

Because of this variety of chip scale packages developed in the industry, one can not make any generalized assumptions on the manufacturability or reliability of the CSP as a homogeneous package group. It is often necessary to determine what the structure of the CSP is before any conclusion on its robustness or manufacturability can be made.

Figure 1. Small size is the main advantage of CSP's. Note

how Xilinx and Philips used a pencil (left) and a cell phone

key pad (right), respectively, to illustrate this.

In an effort to systematically characterize the CSP as a package group, some quarters have come up with four (4) classifications or types for the CSP. These are: 1) the flex circuit interposer type; 2) the rigid substrate interposer type; 3) the custom leadframe type; and 4) the wafer-level assembly type.

The advantages offered by chip scale packages include smaller size (reduced footprint and thickness), lesser weight, relatively easier assembly process, lower over-all production costs, and improvement in electrical performance. CSP's are also tolerant of die size changes, since a reduced die size can still be accommodated by the interposer design without changing the CSP's footprint.

Chip scale packaging can combine the strengths of various packaging technologies, such as the size and performance advantage of bare die assembly and the reliability of encapsulated devices. The significant size and weight reduction offered by the CSP makes it ideal for use in mobile devices like cell phones, laptops, palmtops, and digital cameras.

Figure 2. Example of a Wafer-Level CSP from Maxim;

note the bumps on the die

CSP's are generally built using a lead frame, wherein many devices can be contained on the same substrate, allowing the assembly of many packages in bulk. Doing so maximizes the use of interposer area.

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Wafer-level Packaging; Flip Chip Assembly; BGA; IC Manufacturing; Assembly Equipment

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