Die Stacking; Chip Stacking; Vertical Integration; Stacked Die

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Die Stacking (Page 2 of 2)

Die stacking is fraught with challenges other than those of wirebonding. One of these is the need to keep the stack thermally and mechanically stable on the substrate. At the same time, the resulting package must be as thin as possible, with die interconnections that are electrically good and reliable. Of course, the final thickness of the package depends on the number of die in the stack. As an example, current technology would generally require a 1.4-mm chip scale package (CSP) to accommodate a six-die stack while a four-die stack can fit within a 1.2-mm CSP.

Wafer thinning, thin-wafer handling, and thin die attach are essential elements of successful die stacking. Wafer thinning still involves conventional wafer backgrinding, but it must be followed by a polishing step that relieves stresses imparted by the backgrind process to the wafer. Wafers intended for die stacking can be thinned to just 3-6 mils, depending on the use and the wafer size. Wafers that are this thin are already inherently weak, and require special handling and transport systems to ensure their proper support at all times. Die attach of very thin die, in particular, can be very challenging. The application of preformed tape epoxy on the wafer backside prior to sawing is one technique that facilitates die attach of very thin die.

Figure 2. Side view of wirebonded stacked die;

Photo source: www.kns.com

Another challenge in die stacking is the ability to pick known good die (KGD) from a wafer. The inadvertent use of defective die in die stacking will result in yield losses and higher costs. Unfortunately, wafer-level testing is often not enough to ensure that only KGD's will be picked for die stacking, especially if the device involved is a complex circuit. Thus, poorly yielding wafers that are difficult to test at wafer level are not good candidates for die stacking.

Substrate thickness is also an important factor in die stacking. The thickness of the substrate adds to the over-all package thickness. This means that for a given package height, increasing the substrate thickness will decrease the number of die that can be stacked on it. Stacked die that involve complex devices may require complex substrate routing, which in turn would require additional layers or laminates within the substrate. The core thickness and the number of laminate layers define the over-all substrate thickness. Die stacking should therefore involve some form of substrate engineering to keep the required number of substrate layers and their thicknesses to a minimum.

Die stacking becomes less attractive as the number of die to be stacked increases and as the die involved become more expensive or complex. In such cases, engineers are more inclined to employ package stacking instead of die stacking.

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Primary Reference: http://www.elecdesign.com

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