Semiconductor manufacturing consists of the following steps: 

1) production of silicon wafers from very pure silicon ingots;

2) fabrication of  integrated circuits onto these wafers;

3) assembly of every integrated circuit on the wafer into a finished product; and

4) testing and back-end processing of the finished products.

Wafer Fabrication

Wafer fabrication generally refers to the process of building integrated circuits on silicon wafers.  Prior to wafer fabrication, the raw silicon wafers to be used for this purpose are first produced from very pure silicon ingots, through either the Czochralski (CZ) or the Float Zone (FZ) method. The ingots are shaped then sliced into thin wafers through a process called wafering.

The semiconductor industry has already advanced tremendously that there now exist so many distinct wafer fab processes, allowing the device designer to optimize his design by selecting the best fab process for his device.  Nonetheless, all existing fab processes today simply consist of a series of steps to deposit special material layers on the wafers one at a time in precise amounts and patterns.  Below is an example of what fabricating a simple CMOS integrated circuit on a wafer may entail.

The first step might be to grow a p-type epitaxial layer on the silicon substrate through chemical vapor deposition.  A nitride layer may then be deposited over the epi-layer, then masked and etched according to specific patterns, leaving behind exposed areas on the epi-layer, i.e., areas no longer covered by the nitride layer.  These exposed areas may then be masked again in specific patterns before being subjected to diffusion or ion implantation to receive dopants such as phosphorus, forming n-wells.

Silicon dioxide may then be grown thermally to form field oxides that isolate the n-wells from other parts of the circuit.  This may be followed by another masking/oxidation cycle to grow gate oxide layers over the n-wells intended for  p-channel MOS transistors later on. This gate oxide layer will serve as isolation between the channel and the gate of each of these transistors. Another mask and diffusion/implant cycle may then follow to adjust threshold voltages on other parts of the epi, intended for n-channel transistors later on. 

Deposition of a polysilicon layer over the wafer may then be done, to be followed by a masking/etching cycle to remove unwanted polysilicon areas, defining the polysilicon gates over the gate oxide of the p-channel transistors. At the same time, openings for the source and drain drive-ins are made on the n-wells by etching away oxide at the right locations.

Another round of mask/implant cycle may then follow, this time driving in boron dopants into new openings of the n-wells, forming the p-type sources and drains.   This may then be followed by a mask/implant cycle to form the n-type sources and drains of the n-channel transistors in the p-type epi.

The wafer may then be covered with phospho-silica glass, which is then subjected to reactive ion etching in specific patterns to expose the contact areas for metallization.  Aluminum is then sputtered on the wafer, after which it is subjected to reactive ion etching, also in specific patterns, forming connections between the various components of the circuit.

The wafer may then be covered with glassivation as its top protective layer, after which a mask/etch process removes the glass over the bond pads.

Such is the process of wafer fabrication, consisting of a long series of mask/etch and mask/deposition steps until the circuit is completed.