Silicon on Insulators (SOI)

      

Silicon on Insulators, or SOI, refers to the technology wherein different parts of the device circuit are built on small, separate islands of silicon that are fabricated over insulating substrates, in effect providing a certain degree of isolation between circuits on different islands. The necessary interconnections between these isolated circuits are then achieved using conventional wafer fabrication techniques.  The employment of SOI improves the device's electrical performance by reducing parasitic capacitances, especially in high-speed and very dense circuits.  It also increases radiation hardness for aerospace applications.

            

SOI technology is not new, studies of which go back to as early as the 1960's.  There are several techniques by which SOI implementation may be achieved, but much of the earlier work involves Silicon-on-Sapphire (SOS).  Aside from SOS, techniques for growing single-crystal silicon on various amorphous insulating substrates have also been explored and achieved, although most of these processes never became widely used in VLSI fabrication.

        

One current SOI technology, however, has resulted in MOS and bipolar devices with excellent properties. This involves the use of buried oxide layers, which are basically subsurface layers of silicon dioxide (SiO2) created through ion implantation of very high doses of oxygen.

          

SOS involves the epitaxial growing of silicon on a substrate of sapphire (Al2O3).  This growth is termed 'heteroepitaxy', since the material of the grown layer is different from that of the substrate.  Nonetheless, the equipment and materials used for the heteroepitaxial growth of SOS are essentially identical to those used in homoepitaxial growth.

   

Silane (SiH4) is commonly used as the source of silicon for SOS growth. Its pyrolysis reaction in a carrier hydrogen gas,  SiH4 --> Si + 2H2, results in the deposition of a silicon layer over the sapphire substrate.  The deposition temperature is usually kept below 1050 deg C in order to prevent the autodeposition of aluminum from the sapphire substrate to the silicon layer.  The desired silicon orientation is <100>, which has been achieved on various sapphire orientations, i.e., <1102>, <0112>, <1012>. 

   

As in any technology, SOS has some inherent drawbacks that need to be addressed before its benefits can be realized.  Because of the lattice parameter mismatch between the grown silicon layer and the sapphire substrate, misfit dislocations, edge dislocations, and stacking faults are frequently encountered in SOS devices, with the defect density varying inversely with the distance from the substrate. 

       

The difference between the coefficients of thermal expansion of silicon and sapphire also results in a residual stress within the silicon layer, which tends to reduce hole mobility.  This, coupled with the lower hole and electron mobilities caused by defects, ultimately results in SOS wafers yielding MOS devices with poorer performance in comparison to those fabricated on bulk silicon.

        

SOI fabrication using buried oxide layers follows these basic steps:  1) O2 is implanted  onto the silicon substrate at a high dosage (approx. 2e18 cm-2) and energy (150-300 keV);  2)  an annealing process at a high temperature (1100-1175 deg C) is done in an inert environment (e.g., using N2) for 3-5 hours, achieving two things: restoration of the crystallinity of the substrate surface and formation of the buried oxide itself; and 3) a layer of epitaxial silicon (which will subsequently serve as the layer over which the circuits will be built) is deposited over the buried oxide.  Recently, buried silicon nitride layers (Si3N4) have likewise been successfully used in SOI technology.

       

See Also:  Epitaxy Dielectric IC Manufacturing

 

 

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