The most basic TTL circuit has a single output transistor configured as an inverter with its emitter grounded and its collector tied to Vcc with a pull-up resistor, and with the output taken from its collector. Most TTL circuits, however, use a totem pole output circuit, which replaces the pull-up resistor with a Vcc-side transistor sitting on top of the GND-side output transistor. The emitter of the Vcc-side transistor (whose collector is tied to Vcc) is connected to the collector of the GND-side transistor (whose emitter is grounded) by a diode.  The output is taken from the collector of the GND-side transistor. Figure 1 shows a basic 2-input TTL NAND gate with a totem-pole output.

Figure 1.  A 2-input TTL NAND Gate with a Totem Pole Output Stage

In the TTL NAND gate of Figure 1, applying a logic '1' input voltage to both emitter inputs of T1 reverse-biases both base-emitter junctions, causing current to flow through R1 into the base of T2, which is driven into saturation. When T2 starts conducting, the stored base charge of T3 dissipates through the T2 collector, driving T3 into cut-off.  On the other hand, current flows into the base of T4, causing it to saturate and pull down the output voltage Vo to logic '0', or near ground.  Also, since T3 is in cut-off, no current will flow from Vcc to the output, keeping it at logic '0'.  Note that T2 always provides complementary inputs to the bases of T3 and T4, such that T3 and T4 always operate in opposite regions, except during momentary transition between regions.