The noise margin of a logic gate for logic level '0', Δ0, is defined as the difference between the maximum input voltage that it will recognize as a '0' (Vil) and the maximum voltage that may be applied to it as a '0' (Vol of the gate driving it).  For logic level '1', the noise margin Δ1 is the difference between the minimum input voltage that may be applied to it as a '1' (Voh of the gate driving it) and the minimum input voltage that it will recognize as a '1' (Vih).  Mathematically, Δ0 = Vil-Vol and Δ1 = Voh-Vih.  Any noise that causes a noise margin to be overcome will result in a '0' being erroneously read as a '1' or vice versa.  In other words, noise margin is a measure of the immunity of a gate from reading an input logic level incorrectly.  For TTL, Vil = 0.8V and Vol = 0.4V, so Δ0 = 0.4V, and Voh = 2.4V and Vih = 2.0 V, so Δ1 = 0.4V.  These noise margins are not as good as the noise margins exhibited by DTL.

As mentioned earlier, TTL has a much higher speed than DTL. This is due to the fact that when the output transistor (T4 in Figure 1) is turned off, there is a path for the stored charge in its base to dissipate through, allowing it to reach cut-off faster than a DTL output transistor.  At the same time, the equivalent capacitance of the output is charged from Vcc through T3 and the output diode, allowing the output voltage to rise more quickly to logic '1' than in a DTL output wherein the output capacitance is charged through a resistor.  

The commercial names of digital IC's that employ TTL start with '74', e.g., 7400, 74244, etc. Most TTL devices nowadays, however, are named '74LSXXX', with the 'LS' standing for 'low power Schottky'.  Low power schottky TTL devices employ a Schottly diode, which is used to limit the voltage between the collector and the base of a transistor, making it possible to design TTL gates that use significantly less power to operate while allowing higher switching speeds.  See also:  CMOS circuits.