Failures due to Wafer Crystal Defects
Crystallographic defects that are present in silicon wafers do affect
the electrical performance of devices built onto these wafers. Important
device properties that are impacted by defects within the silicon
crystal include: 1)
minority carrier lifetimes;
2) leakage currents in p-n junctions; 3)
collector-emitter leakage currents in bipolar transistors; 4) MOS gate oxide quality; and 5) MOS threshold voltages.
Extreme cases of degradation due to the presence of these defects can
result in device failures.
refers to the average time interval between the generation and
recombination of a minority carrier (electrons in p-type silicon and
holes in n-type silicon) in a semiconductor crystal.
which involves a free electron and a hole combining to annihilate each
is a process by which carriers return to their inactive state, e.g., the electron falls from the conduction band back to the valence band
where it can no longer conduct. The minority carrier lifetime
affects the performance of the device in many ways, although generally
(but not exclusively) a longer minority carrier lifetime is desired.
of defects and electrically neutral impurities in the crystal decreases
the minority carrier lifetime, since these defects and impurities tend
to form recombination centers within the crystal that 'trap' active
carriers. These recombination centers are actually additional
localized intermediate energy levels within the semiconductor
bandgap, which is
the separation between the lowest conduction band energy level and the
highest valence band energy level. Imperfections that introduce such
intermediate energy levels include point defects, clusters of point
defects, and dislocations.
Reverse-biased p-n junctions are supposed to be non-conducting, and must
therefore exhibit as little leakage current as possible. Excessive
can have various detrimental effects: the device's power dissipation may
increase, DRAM storage stability may degrade, device voltage/current
characteristics may shift, etc.
defects that can result in increased
are transition metal precipitates and dislocations. Dislocations
that are decorated by electrically active metal impurities can appear
across the junction and cause it to exhibit excessive current leakage.
Dislocations and the strain caused by accumulating precipitates in the
p-n junction can also form carrier generation-recombination centers that
may lead to higher current leakage.
common device problem that is attributed to crystal defects is increased
bipolar transistors. The interesting aspect of this issue is the
fact that the collector-base and base-emitter leakage currents may
remain at minimal levels, even while there is a marked increase in
collector-emitter leakage. Thus, in such a degradation, a certain amount
of current flows from collector to emitter even if there's no current
flowing into the base.
leakages have been
attributed to several types of crystal defects. For instance, a dislocation
that passes through the transistor from the collector to the emitter, if
can allow appreciable current to flow between the collector and emitter
even if the base current is zero. Diffusion may also be
enhanced along such a dislocation during emitter formation, contributing
to the collector-emitter leakage current. Dislocations that increase
collector-emitter current leakage by way of enhanced diffusion are known
as 'collector pipes.'
Collector pipes in bipolar transistors,
which result in significant collector-emitter leakage currents even in
the absence of a base current,
have been subjected to numerous studies using electron-beam-induced
current (EBIC) techniques.
The gate oxides of MOS
devices must exhibit minimal oxide leakage current and high oxide
Stacking faults in the silicon substrate, usually caused by
metallic contamination during oxidation, have been shown by studies to
increase gate oxide current leakage and lower the gate oxide's breakdown
voltage. Higher gate oxide defect density, which also reduces the
oxide's breakdown voltage, has also been correlated with the presence of
oxygen precipitates at the wafer surface.
The threshold voltages of
MOS transistors on a wafer depend on the
resistivity of the wafer
substrate. Keeping these threshold voltages within the required
specifications is important to proper device operation.
Wafer-to-wafer variability in resistivity can be caused by temperature
fluctuations when the silicon ingot was produced, or by alterations in
the carrier concentrations resulting from the presence of oxygen
Wolf and Tauber, Silicon Processing for the VLSI Era Vol. 1, Lattice
Silicon Wafers; Crystal
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