Wafer-Level Packaging; WLP

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Wafer-Level Packaging (Page 3 of 3)

Encapsulated Beam technology includes a very diverse class of WLP techniques from wafer lamination to glass technology. Examples of this technology are Shellcase's ShellBGA™ and ShellOp™, and Tessera's WAVE™.

Shellcase's patented ShellBGA™ is a true chip-size BGA type of wafer-level package wherein the silicon chip or die is sandwiched between two glass layers, resulting in a thin glass-silicon-glass structure. The glass sheet covering the active surface of the wafer has openings for the solder balls. The glass sheet covering the die backside completes the total enclosure of the die. Note that the die is completely encapsulated in epoxy prior to its being laminated between the two glass sheets.

Shellcase's ShellOP™, is similar to ShellBGA™, except that the solder balls are located on the die backside. This allows a clear view of the die's active circuit through the clear glass sheet protecting the top surface. This type of package was designed for image sensing and light detection applications, which is why it was designed to provide the die circuit with unobstructed exposure to external light. The die's bond pads are routed to the backside glass sheet which has openings to accommodate the solder balls.

Tessera's WAVE™ package ('WAVE' stands for "Wide Area Vertical Expansion") is a WLP technology targeting high I/O applications that require short assembly cycle time. The interconnection routing used by this architecture comes in the form of a compliant polyimide film-based copper circuit.

This polyimide film circuit is accurately aligned and brought into contact with the wafer, after which a low-modulus encapsulant is forced into the small space between the polyimide film and the wafer. This process causes both the polyimide film and wafer to expand, resulting in the polyimide bases' copper conductors to transform into its intended shape, i.e., as a stress-absorbing structure that links the die to the interposer. The wafer-level packaging is then completed with encapsulation and solder ball attachment steps.

The main drivers of WLP technology in the semiconductor industry today are cost, size, test, and burn-in. The advantages offered by wafer-level packaging include:

1) space savings from attainment of the smallest package possible for a device, i.e., a true chip-size package;

2) lowest cost per I/O since the traditional package assembly processes that are independent of wafer fab have been replaced by wafer-level interconnection processes;

3) lowest cost of electrical testing since this is done more efficiently at wafer level;

4) lowest cost of burn-in since this is done more efficiently at wafer level;

5) enhancement of device performance because of its minimum-length interconnections;

6) elimination of the need for underfilling of solder joints with organic materials; and

7) easier inventory management since fab, assembly, test, and burn-in can essentially be housed under one production floor.

As of this writing (2004), wafer-level packaging technology still has lots of room for improvement. Its range of applications is not yet too encompassing, being currently applied primarily to small packages with low I/O count, such as those used in analog/linear IC's, certain types of memories, integrated passive devices, and certain types of controllers.

Also, given the multitude of technologies available as WLP solutions today, we might not see a single industry-standard 'best-known' WLP process in the near future. Most experts likewise agree that WLP will not be the exclusive solution of choice for the packaging requirements of the future. Still, there's reason to believe that WLP technology will advance and become more cost-effective to eventually find its way into more complex, higher I/O applications in the electronics industry.

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