Wafer-Level Test and Burn-in (WLTBI)

Custom Search

Wafer-level Test and Burn-in (WLB)

Wafer-level Test and Burn-in (WLTBI) refers to the process of subjecting semiconductor devices to electrical testing and burn-in while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life failures.

WLTBI usually employs a wafer prober to supply the necessary electrical excitation to all the die on the wafer through hundred or thousands of ultrathin probing needles that land on the bond pads, balls, or bumps on the die. The required die temperature elevation, on the other hand, is achieved by the wafer prober through a built-in hot plate that heats up the wafer to the correct junction temperature.

Wafer-level testing and burn-in is applicable not only to: 1) devices sold as bare die, which are also referred to as 'known good die' or 'KGD'; and 2) wafer-level packaged devices; but to 3) devices intended for conventional packaging as well. In the third case, WLTBI is performed as a prescreen, so that only the parts that passed WLTBI will undergo back-end processing, i.e., assembly and final test.

The ideal semiconductor manufacturing scenario is to come up with a process that does everything at wafer level, but its prohibitive costs for now does not make it viable for all applications just yet. Once perfected, however, an integrated wafer-level packaging, wafer-level electrical testing, and wafer-level burn-in will streamline the over-all semiconductor manufacturing process to a large degree, resulting in great cost savings and much shorter cycle times.

After all, wafer-level packaging, which is basically just an extension of the traditional wafer fabrication process to provide each die on the wafer with a means of interconnecting to the outside world, would eliminate the need for a separate IC packaging/assembly line. In a similar fashion, wafer-level testing and wafer-level burn-in would eliminate the need for separate equipment for testing and burn-in, since both of them may be performed on a wafer using the same basic methodology and set-up.

This is not so in the case of individually packaged IC's, whose electrical testing and burn-in require different equipment in different areas on the production floor. Conventional electrical testing uses expensive automated test equipment (ATE) on the test floor while conventional burn-in requires burn-in ovens that are kept in their own burn-in areas due to the large amounts of heat that they radiate.

Still, the basic philosophies used in testing and burning in individual IC's are the same as those used for wafer-level test and burn-in. Both electrical testing and burn-in need a means of supplying the devices under test (DUT) with electrical bias and excitation, whether it's done at wafer level or at package level. The difference lies in the method of delivering the required electrical bias and excitation to the devices.

During electrical testing of individual IC's, electrical bias and excitation are provided by the ATE to the DUT by mechanically contacting its leads. In conventional burn-in of individual IC's, the units are placed on burn-in boards which in turn are inserted inside burn-in ovens. The burn-in ovens provide the electrical bias and excitation needed by the devices during burn-in through these burn-in boards.

During wafer-level testing and burn-in, however, the electrical bias and excitation required by the devices are delivered directly to the interconnection points (the bond pads or the solder balls/bumps over the bond pads) of each die on the wafer. This can be achieved in a variety of ways, some of which are discussed in the next page.

<Proceed to Page 2 - Achieving Full Wafer Contact>

<Proceed to Page 3 - Challenges in Wafer Level Test and Burn-in>

See Also: Electrical Testing; Burn-in; Probe/Trim;

Wafer-Level Packaging; IC Manufacturing

HOME