Wafer-Level Test and Burn-in (WLTBI) - Page 2 of 3: Achieving Full Wafer Contact

Custom Search

Wafer-level Test and Burn-in (WLB) - Page 2 of 3

Achieving Full Wafer Electrical Contact

The challenge in any wafer-level testing and burn-in process is being able to use existing wafer probing technology to contact all the operation-essential pads of all the die on the wafer at the same time. This is referred to as full-wafer or whole-wafer contact technology. The capability to do so will allow the burn-in process to be conducted to the entire wafer in one operation.

Once electrical contacts have been made, wafer-level devices may already be subjected to the same testing methodology as what their individually packaged counterparts normally receive. In electrical testing, this may mean subjecting the DUT to a sequence of test blocks, each of which forces a certain set of voltage and/or current conditions to the DUT and measures the corresponding current/voltage/timing response of the DUT against specifications.

Burn-in, on the other hand, places the DUT in an electrically stressful condition over a specified amount of time. Stressful electrical conditions include operating the device at maximum power dissipation, continuous dynamic switching of the inputs, application of high reverse bias voltages, and the like.

In an article by Dan Inbar and Mark Murin of M-Systems (source: Semiconductor International, 8/1/2004), the formidability of achieving whole-wafer contact with today's wafers was explained using a simple example: if a typical wafer has 500 die, with each die containing 40 functional pads, then 20,000 probing points are needed to properly activate all of these die on the wafer during burn-in. Cramming all of these probe needles onto a single 6" wafer at the same time without allowing any of them to come into contact is indeed challenging.

Full-wafer contact systems currently employ three different methods or technologies: 1) the probe-per-pad method; 2) the sacrificial metal method; and 3) the built-in test/burn-in method.

The example above wherein each pad of each die on the wafer is directly contacted by an ultra-thin contact pin or needle of a wafer probing system so that electrical testing may be performed by the test equipment pertains to the probe-per-pad method. Needless to say, the challenge presented by this method is coming up with a proper design for an extremely dense array of probes.

In the sacrificial metal method, a thin layer of metal is deposited over the entire wafer in patterns that connect together the equivalent bond pads of groups of die on the wafer, so that a reduced number of probe needles may be used to excite all the die on the wafer. After the WLTBI process is completed, this sacrificial layer is etched away from the wafer. The main drawback of this method is the need for extra wafer fab steps to deposit and remove the sacrificial metal layer.

The built-in test/burn-in method involves the application of Design-for-Test (DFT) philosophy in the development of new products. Here, a new device would incorporate an additional special circuit on the die that would facilitate self-testing and/or self-burn-in using a relatively smaller number of probes. Such a circuit might employ serial I/O (to reduce the number of I/O probes needed) and a built-in test/burn-in subsystem. Wafers of this new product may then undergo full-wafer contact probing using a much smaller number of probes.

<Proceed to Page 3 - Challenges in Wafer Level Test and Burn-in>

<Back to Page 1 - Intro to Wafer Level Test and Burn-in>

See Also: Electrical Testing; Burn-in; Probe/Trim;

Wafer-Level Packaging; IC Manufacturing

HOME